The present invention relates to a control apparatus and method, and more particularly, to an apparatus and method for controlling supply of a clock signal to a memory device.
FIG. 1 is a block diagram of a system 10 including a memory device 40 and a conventional controller 20. FIG. 2 is a timing diagram of signals output from a master that interfaces with the memory device 40 illustrated in FIG. 1. Referring to FIGS. 1 and 2, the system 10 includes a controller 20, the memory device 40, a first host 50 and a second host 52.
The controller 20 includes first through fourth masters 22, 24, 26, and 28, an arbiter 30, a first slave 32, a second slave 34, and a bus 36. It is assumed for purposes of this description that the first slave 32 is a data random-access memory (RAM) that stores data exchanged with the third master 26, and the second slave 34 is a data RAM that stores data exchanged with the fourth master 28.
As the first through fourth masters 22, 24, 26, and 28 share the bus 36 in the controller 20, they may access the bus 36 according to a priority protocol controlling use or ownership of the bus 36. The arbiter 30 arbitrates the priority of use of the bus 36 between the first through fourth masters 22, 24, 26, and 28 according to a specified method or protocol, such as a fixed priority method or a round-robin method. Accordingly, while one of the first through fourth masters 22, 24, 26, and 28 uses the bus 36, the other masters must wait for some time period until they obtain priority to use of the bus 36.
If the first host 50 exchanges a large amount of data, e.g., 2 KB of data, with the memory device 40 through the third master 26, the first slave 32, and the second master 24 using the bus 36, the second master 24 may need to use/control the bus 36 for a long period of time. Also, when the second host 52 exchanges a large amount of data with the memory device 40 via the fourth master 28, the second slave 34, and the second master 24 using the bus 36, the second master 24 may also need to use/control the bus 36 for a long period of time.
However, when a master (e.g., the first master 22) having higher priority than the second master 24 requests the arbiter 30 allow it to use/control the bus 36 and uses the bus 36, the second master 24 must wait for a period of time until the first master 22 loses the ownership of the bus 36. That is, when a master (e.g., the first master 22) having higher priority than the second master 24 requests the use of the bus 36, the second master 24 generally stores a predetermined address ADD of currently transmitted data A, B, . . . , C in a predetermined storage device, transfers the ownership of the bus 36 to the first master 22, and waits for a period of time until the higher priority master loses the ownership of the bus 36.
Referring to FIG. 2, when the second master 24 regains the ownership of the bus 36, the second master 24 of the controller 20 and the memory device 40 generally must be reset to transmit the remaining data D, E, . . . , G. Then, the second master 24 may transmit the address following the address of the already transmitted data (e.g., data C) to the memory device 40, and exchange the remaining data D, E, . . . , G with the memory device 40. As a result, the data transmission performance (efficiency) between the second master 24 of the controller 20 having the first through fourth 22, 24, 26, and 28, and the memory device 40 may be significantly lowered.
Also, even if data cannot be exchanged between the second master 24 of the controller 20 and the memory device 40 (for example, when the second master 24 loses the ownership of the bus 36), the second master 24 typically continuously supplies a clock signal CLK to the memory device 40, which may cause unnecessary consumption of power in the second master 24 and the memory device 40.